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fn7347 rev 2.00 page 1 of 14 may 20, 2005 fn7347 rev 2.00 may 20, 2005 EL8300 200mhz rail-to-rail amplifier datasheet the EL8300 represents a triple rail-to-rail amp lifier with a - 3db bandwidth of 200mhz an d slew rate of 200v/s. running off a very low supply current of 2ma per channel, the EL8300 also featur es inputs that go to 0.15v below the v s - rail. the EL8300 includes a fast-acting disable/power-down circuit. with a 25ns disable and a 200ns enable, the EL8300 is ideal for multiple xing applications. the EL8300 is designed for a number of general purpose video, communication, instrumentation, and industrial applications. the EL8300 is ava ilable in an 16-pin so and 16-pin qsop packages and is sp ecified for operation over the -40c to +85c temperature range. pinout EL8300 (16-pin so, qsop) top view features ? 200mhz -3db bandwidth ? 200v/s slew rate ? low supply current = 2ma per amplifier ? supplies from 3v to 5.5v ? rail-to-rail output ? input to 0.15v below v s - ? fast 25ns disable ? low cost ? pb-free pus anneal ava ilable (rohs compliant) applications ? video amplifiers ? portable/hand-held products ? communications devices ina+ cea vs- ceb inb+ nc cec inc+ ina- outa vs+ outb inb- nc outc inc- - + 1 2 3 4 16 15 14 13 5 6 7 12 11 10 8 9 - + - + ordering information part number package tape & reel pkg. dwg. # EL8300is 16-pin so - mdp0027 EL8300is-t7 16-pin so 7 mdp0027 EL8300is-t13 16-pin so 13 mdp0027 EL8300isz (see note) 16-pin so (pb-free) - mdp0027 EL8300isz-t7 (see note) 16-pin so (pb-free) 7 mdp0027 EL8300isz-t13 (see note) 16-pin so (pb-free) 13 mdp0027 EL8300iu 16-pin qsop - mdp0040 EL8300iu-t7 16-pin qsop 7 mdp0040 EL8300iu-t13 16-pin qsop 13 mdp0040 EL8300iuz (see note) 16-pin qsop (pb-free) - mdp0040 EL8300iuz-t7 (see note) 16-pin qsop (pb-free) 7 mdp0040 EL8300iuz-t13 (see note) 16-pin qsop (pb-free) 13 mdp0040 note: intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible wit h both snpb and pb-free soldering operations. intersil pb-free product s are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020.
EL8300 fn7347 rev 2.00 page 2 of 14 may 20, 2005 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maximum ratings (t a = 25c) supply voltage from v s + to v s - . . . . . . . . . . . . . . . . . . . . . . . . 5.5v input voltage . . . . . . . . . . . . . . . . . . . . . . . . v s + +0.3v to v s - -0.3v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v continuous output current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ma power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +125c ambient operating temperature . . . . . . . . . . . . . . . .-4 0c to +85c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . +125c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. electrical specifications v s + = 5v, v s - = gnd, t a = 25c, v cm = 2.5v, r l to 2.5v, a v = 1, unless otherwise specified parameter description conditions min typ max unit input characteristics v os offset voltage -5 -0.8 +5 mv tcv os offset voltage temperature coefficient measured from t min to t max 3v/c ib input bias current v in = 0v -3 -1.4 a i os input offset current v in = 0v 0.2 0.55 a tci os input bias current temperature coefficient measured from t min to t max 2na/c cmrr common mode rejection ratio v cm = -0.15v to +3.5v 70 90 db cmir common mode input range v s - - 0.15 v s + - 1.5 v r in input resistance common mode 16 m ? c in input capacitance 0.5 pf a vol open loop gain v out = +1.5v to +3.5v, r l = 1k ? to gnd 75 90 db v out = +1.5v to +3.5v, r l = 150 ? to gnd 80 db output characteristics r out output resistance a v = +1 30 m ? v op positive output voltage swing r l = 1k ? 4.85 4.88 v r l = 150 ? 4.65 4.68 v v on negative output voltage swing r l = 150 ? 150 200 mv r l = 1k ? 50 65 mv i out linear output current 65 ma i sc (source) short circuit current r l = 10 ? 50 75 ma i sc (sink) short circuit current r l = 10 ? 90 130 ma power supply psrr power supply rejection ratio v s + = 4.5v to 5.5v 70 100 db i s-on supply current - enabled per amplifier 2 2.6 ma i s-off supply current - disabled per amplifier 40 90 a enable t en enable time 200 ns t ds disable time 25 ns v ih-enb enable pin voltage for power-up 0.8 v v il-enb enable pin voltage for shut-down 2 v
EL8300 fn7347 rev 2.00 page 3 of 14 may 20, 2005 i ih-enb enable pin input current high 8.6 a i il-enb enable pin input for current low 0.01 a ac performance bw -3db bandwidth a v = +1, r f = 0 ? , c l = 1.5pf 200 mhz a v = -1, r f = 1k ? , c l = 1.5pf 90 mhz a v = +2, r f = 1k ? , c l = 1.5pf 90 mhz a v = +10, r f = 1k ? , c l = 1.5pf 10 mhz bw 0.1db bandwidth a v = +1, r f = 0 ? , c l = 1.5pf 20 mhz peak peaking a v = +1, r f = 1k ? , c l = 5pf 1 db gbwp gain bandwidth product 100 mhz pm phase margin r l = 1k ? , c l = 1.5pf 55 sr slew rate a v = 2, r l = 100 ? , v out = 0.5v to 4.5v 160 200 v/s t r rise time 2.5v step , 20% - 80% 8 ns t f fall time 2.5v step , 20% - 80% 7 ns os overshoot 200mv step 10 % t pd propagation delay 200mv step 2 ns t s 0.1% settling time 200mv step 20 ns dg differential gain a v = +2, r f = 1k ? , r l = 150 ? 0.035 % dp differential phase a v = +2, r f = 1k ? , r l = 150 ? 0.05 e n input noise voltage f = 10khz 10 nv/ ? hz i n + positive input noise current f = 10khz 1 pa/ ? hz i n - negative input noise current f = 10khz 0.8 pa/ ? hz e s channel separation f = 100khz 95 db electrical specifications v s + = 5v, v s - = gnd, t a = 25c, v cm = 2.5v, r l to 2.5v, a v = 1, unless otherwise specified (continued) parameter description conditions min typ max unit pin descriptions pin name function 1, 5, 8 ina+, inb+, inc+ non-inverting input for each channel 2, 4, 7 cea , ceb , cec enable and disable input for each channel 3 vs- negative power supply 6, 11 nc not connected 9, 12, 16 inc-, inb-, ina- inverting input for each channel 10, 13, 15 outc, outb, outa amplifier output for each channel 14 vs+ positive power supply
EL8300 fn7347 rev 2.00 page 4 of 14 may 20, 2005 typical performance curves figure 1. frequency response for various output voltage levels figure 2. small signal f requency response for various r load figure 3. small signal frequency response for various non-inverting gains figure 4. small signal f requency response for various inverting gains figure 5. small signal frequency response for various c l figure 6. small signal f requency response for various c l 4 2 0 -2 -4 -6 100k 1m 10m 100m 1g frequency (hz) gain (db) v s =5v a v =1 r l =1k ? c l =1.5pf v op-p =200mv v op-p =1v v op-p =2v 4 2 0 -2 -4 -6 100k 1m 10m 100m 1g frequency (hz) gain (db) v s =5v a v =1 c l =1.5pf r l =330 ? r l =1k ? r l =100 ? ?? ?? ? c l =1.5pf a v =1 a v =10 a v =5 a v =2 4 2 0 -2 -4 -6 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) v s =5v r l =1k ? c l =1.5pf r f =1k ? a v =-10 a v =-2 a v =-5 5 3 1 -1 -3 -5 100k 1m 10m 100m 1g frequency (hz) gain (db) v s =5v a v =1 r l =1k ? v op-p =200mv c l =10pf c l =7pf c l =5pf c l =1.5pf 14 10 6 2 -2 -6 100k 1m 10m 100m 1g frequency (hz) gain (db) c l =15pf c l =1.5pf c l =56pf c l =35pf v s =5v a v =2 r l =1k ? r f =r g =1k ? -12 -8 -4 0 4
EL8300 fn7347 rev 2.00 page 5 of 14 may 20, 2005 figure 7. small signal frequency response for various r f and r g figure 8. open loop gain and phase vs frequency figure 9. common-mode rejection ratio vs frequency figure 10. small signal bandwidth vs supply voltage figure 11. output impedance vs frequency figure 12. small signal p eaking vs supply voltage typical performance curves (continued) 10 8 6 4 2 0 100k 1m 10m 100m 1g frequency (hz) gain (db) v s =5v a v =2 r l =1k ? c l =1.5pf r f =r g =2k ? r f =r g =500 ? r f =r g =1k ? ?? ?? ? phase () -45 405 315 225 135 45 100k 10m r l =150 ? r l =150 ? r l =1k ? ?? ?? ?? ??? ? c l =1.5pf a v =1 a v =2 190 110 90 150 4 100 10 1 0.1 0.01 10k 100k 1m 10m frequency (hz) impedance ( ? ) 100m 2.5 1 2 0 3 3.5 4.5 5 5.5 v s (v) peaking (db) a v =1 r l =1k ? c l =1.5pf 1.5 0.5 4
EL8300 fn7347 rev 2.00 page 6 of 14 may 20, 2005 figure 13. power supply rejection ratio vs frequency figure 14. harmonic distortion vs output voltage figure 15. disabled output isolation frequency response figure 16. harmonic distortion vs frequency figure 17. harmonic distortion vs load resistance figure 18. voltage and current noise vs frequency typical performance curves (continued) -10 -30 -50 -70 -90 -110 1k 10k 10m 100m frequency (hz) psrr (db) 100k 1m psrr- psrr+ -45 -65 -75 -55 -95 15 v op-p (v) distortion (dbc) v s =5v r l =1k ? c l =1.5pf a v =2 -85 34 2 h d 2 @ 1 0 m h z h d 3 @ 1 0 m h z h d 3 @ 5 m h z h d 2 @ 5 m h z h d 2 @ 1 m h z hd3@1mhz -10 -30 -50 -70 -90 -110 1k 10k 1m 100m 1g frequency (hz) gain (db) v s =5v a v =1 r l =1k ? c l =1.5pf 10m 100k -30 -50 -80 -40 -100 140 frequency (mhz) distortion (dbc) v s =5v r l =1k ? v o =1v p-p for a v =1 v o =2v p-p for a v =2 -90 10 h d 2 @ a v = 2 -70 -60 h d 2 @ a v = 1 h d 3 @ a v = 2 h d 3 @ a v = 1 -60 -75 -90 -65 -100 100 2k r load ( ? ) distortion (dbc) -95 1k v s =5v v o =1v p-p for a v =1 v o =2v p-p for a v =2 -70 -85 -80 h d 2 @ a v = 2 h d 2 @ a v = 1 h d 3 @ a v = 2 h d 3 @ a v = 1 1k 1 100 0.1 10 100 10k 100k 10m frequency (hz) voltage noise (nv/ ? hz) current noise (pa/ ? hz) e n 10 1k 1m i n + i n -
EL8300 fn7347 rev 2.00 page 7 of 14 may 20, 2005 figure 19. channel separation vs frequency figure 20. large sign al transient response figure 21. output swing figure 22. small sig nal transient response figure 23. output swing figure 24. disabled response typical performance curves (continued) -10 -30 -50 -70 -100 100k 1m 10m 100m 1g frequency (hz) channell separation (db) -20 -40 -60 -80 -90 ch1<=>ch2 ch2<=>ch3 ch1<=>ch3 v s =5v, a v =1, r l =1k ? to 2.5v 10ns/div 0 5 2.5 v s =5v, a v =5, r l =1k ? to 2.5v 2s/div 0 5 2.5 v s =5v, a v =1, r l =1k ? to 2.5v c l =1.5pf 10ns/div 2.4 2.5 2.6 v s =5v, a v =5, r l =1k ? to 2.5v 2s/div 0 5 2.5 v s =2.5v, a v =1, r l =1k ? ch1, ch2, 0.5v/div, m=20ns ch2 ch1 enable input output
EL8300 fn7347 rev 2.00 page 8 of 14 may 20, 2005 figure 25. enabled response figure 26. package power dissipation vs ambient temperature figure 27. package power dissipation vs ambient temperature typical performance curves (continued) v s =2.5v, a v =1, r l =1k ? ch1, ch2, 1v/div, m=100ns ch2 ch1 enable input v out 633mw ? j a =1 5 8 c / w q s o p 1 6 1.2 1 0.8 0.6 0.4 0 0 255075100 150 ambient temperature (c) power dissipation (w) 125 85 jedec jesd51-3 low effective thermal conductivity test board 0.2 ? j a = 1 1 0 c / w s o 1 6 ( 0 . 1 5 0 ) 909mw 893mw ? j a = 1 1 2 c / w q s o p 1 6 1.4 1.2 1 0.8 0.6 0.2 0 0 255075100 150 ambient temperature (c) power dissipation (w) 125 85 jedec jesd51-7 high effective thermal conductivity test board 0.4 1.250w ? j a = 8 0 c / w s o 1 6 ( 0 . 1 5 0 )
EL8300 fn7347 rev 2.00 page 9 of 14 may 20, 2005 simplified schematic diagram description of operat ion and application information product description the EL8300 is wide bandwidth, single supply, low power and rail-to-rail output voltage feed back operational amplifier. the amplifiers are internally comp ensated for closed loop gain of +1 of greater. connected in voltage follower mode and driving a 1k ? load, the EL8300 has a -3db bandwidth of 200mhz. driving a 150 ? load, the bandwidth is about 130mhz while maintaining a 200v/us slew rate . the EL8300 is available with a power down pin for each cha nnel to reduce power to 30a typically while the amplifier is disabled. input, output and supply voltage range the EL8300 has been designed to operate with a single supply voltage from 3v to 5. 0v. split supplies can also be used as long as their total voltage is w ithin 3v to 5.0v. the amplifier s have an input common mode volt age range from 0.15v below the negative supply (v s - pin) to within 1.5v of the positive supply (v s + pin). if the input signal is outside the above specified range, it will cause the output signal to be distorte d. the output of the EL8300 can swin g rail to rail. as the load resistance becomes lower, the ability to drive close to each ra il is reduced. for the load resistor 1k ? , the output swing is about 4.9v at a 5v supply. fo r the load resistor 150 ? , the output swing is about 4.6v. choice of feedback resistor and gain bandwidth product for applications that require a gain of +1, no feedback resisto r is required. just short the output pin to the inverting input p in. for gains greater t han +1, the feedback re sistor forms a pole with the parasitic capacitance at the inverting input. as this pole becomes smaller, the amplifiers phase margin is reduced. this causes ringing in the time domain and peaking in the frequency domain. therefore, r f has some maximum value that should not be exceeded fo r optimum perf ormance. if a large value of r f must be used, a small capacitor in the few pico farad range in parallel with r f can help to reduce the ringing and peaking at the ex pense of reducing the bandwidth. as far as the output stage of t he amplifier is concerned, the output stage is also a ga in stage with the load. r f and r g appear in parallel with r l for gains other than +1. as this combination gets smaller, the bandwidth falls off. consequently, r f also has a minimum value that should not be exceeded for optimum perfo rmance. for gain of +1, r f =0 is optimum. for the gains other t han +1, optimum response is obtained with r f between 300 ? to 1k ? . the EL8300 has a gain bandwid th product of 100mhz. for gains ? 5, its bandwidth can be predicted by the following equation: video performance for good video performance, an amplifier is required to maintain the same output i mpedance and the same frequency response as dc levels are cha nged at the output. this is especially difficult when driving a standard video load of 150 ? , because the change in output current wit h dc level. special circuitry has been incorporate d in the EL8300 to reduce the variation of the output impedance with the current output. this results in dg and dp specif ications of 0.03% and 0.05 ? , while driving 150 ? at a gain of 2. driving high impedance loads would give a similar or be tter dg and dp performance. driving capacitive loads and cables the el8100, el8101 can drive 1 0pf loads in parallel with 1k ? with less than 5db of peaking at gain of +1. if less peaking is desired in applications, a small series resistor (usually betwe en 5 ? to 50 ? ) can be placed in series with the output to eliminate in+ in- i 1 i 2 r 6 r 3 r 1 r 2 q 1 q 2 r 7 v bias1 q 5 q 6 r 8 q 7 q 8 r 9 q 3 q 4 r 4 r 5 v s- out v bias2 v s+ differential to drive generator single ended gain bw ? 100mhz =
EL8300 fn7347 rev 2.00 page 10 of 14 may 20, 2005 most peaking. however, this will reduce the gain slightly. if t he gain setting is greater than 1, the gain resistor r g can then be chosen to make up for any gain loss which may be created by the additional series r esistor at the output. when used as a cable driver, double termination is always recommended for reflection-free performance. for those applications, a back-terminati on series resistor at the amplifiers output will isolate the amplifier from the cable an d allow extensive capacitive drive . however, other applications may have high capaci tive loads without a back-termination resistor. again, a small series resistor at the output can help to reduce peaking. disable/power-down the EL8300 can be di sabled and placed its output in a high impedance state. the turn off time for each channel is about 25ns and the turn on time is about 200ns. when disabled, the amplifiers supply current is re duced to 30a typ ically, thereb y effectively eliminating the powe r consumption. the amplifiers power down can be controlled by standard ttl or cmos signal levels at the enable pin. the applied logic signal is relative to v s - pin. letting the enable pin float or applying a signal that is less than 0.8v above v s - will enable the amplifier. the amplifier will be disabled when the signal at enable pin is 2v above v s -. output drive capability the EL8300 does not have internal short circuit protection circuitry. they have a typical short circuit current of 70ma sourcing and 140ma sinking for the output is connected to half way between the r ails with a 10 ? resistor. if the output is shorted indefinitely, the power dissipation could easily increa se such that the part will be destr oyed. maximum reliability is maintained if the output curre nt never exceeds 40ma. this limit is set by the design of the internal metal interconnectio ns. power dissipation with the high output drive cap ability of the EL8300, it is possible to exceed the 125 ? c absolute maximum junction temperature under certain load current conditions. therefore, i t is important to calculate the ma ximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the sa fe operating area. the maximum power dissipation allowed in a package is determined according to: where: t jmax = maximum juncti on temperature t amax = maximum ambient temperature ? ja = thermal resistance of the package the maximum power dissipation actually produced by an ic is the total quiescent supply curr ent times the total power supply voltage, plus the power in the ic due to the load, or: for sourcing: for sinking: where: v s = total supply voltage i smax = maximum quiesce nt supply current v outi = maximum output voltage of the application for each channel r loadi = load resistance tied to ground for each channel i loadi = load current f or each channel by setting the two pd max equations equal to each other, we can solve the output current and r loadi to avoid the device overheat. power supply bypassing and printed circuit board layout as with any high frequency device, a good printed circuit board layout is necessary f or optimum perform ance. lead lengths should be as sort as possible. the power supply pin must be well bypassed to reduce the ri sk of oscillati on. for normal single supply operation, where the v s - pin is connected to the ground plane, a single 4.7f tant alum capacitor in parallel wit h a 0.1f ceramic c apacitor from v s + to gnd will suffice. this same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. in this case, t he v s - pin becomes the ne gative supply rail. for good ac performance, paras itic capacitance should be kept to a minimum. u se of wire wound re sistors should be avoided because of their additi onal series inductance. use of sockets should also be avoided if possible. sockets add parasitic inductance and capacitance that can result in compromised performance. minimizing parasitic capacitance at the amplifiers inverting inpu t pin is very important. the feedback resistor should be place d very close to the inverting input pin. strip line design te chniques are recommended for the signal traces. typical applications video sync pulse remover many cmos analog to digital converters have a parasitic latch up problem when subjected to negative input voltage levels. since the sync tip contains no useful video information and it is pd max t jmax t amax C ? ja -------------------------------------------- - = pd max v s i smax v s v outi C ?? v outi r li ----------------- ? i1 = 3 ? + ? = pd max v s i smax v outi v s - C ?? i loadi ? i1 = 3 ? + ? =
EL8300 fn7347 rev 2.00 page 11 of 14 may 20, 2005 a negative going pulse , we can chop it off. figure 28 shows a gain of 2 connections for EL8300. figure 29 shows the complete input video signal applie d at the input, as well as th e output signal with th e negative going sync pulse removed. multiplexer besides the normal power down usage, the enable pin of the EL8300 can be used for multipl exing applications. figure 30 shows two channels wit h the outputs tied t ogether, driving a back terminated 75 ? video load. a 2v p-p 2mhz sine wave is applied to amp a and a 1v p-p 2mhz sine wave is applied to amp b. figure 31 shows the enable signal and the resulting output waveform at v out . observe the break-before-make operation of the multiplex ing. amp a is on and v in1 is passed through to the output when the enable signal is low and turns off in about 25ns when the enable signal is high. about 200ns later, amp b turns on and v in2 is passed through to the output. the break-before-make operation ensures that more than one amplifier isnt trying to drive the bus at the same ti me. single supply video line driver the EL8300 is wideband rail-to-ra il output op amplifiers with large output current, excellent d g, dp, and low distortion that allow them to drive video signals in low supply applications. figure 32 is the single supply n on-inverting video line driver configuration and fi gure 33 is the invert ing video ling driver configuration. the signal is ac coupled by c 1 . r 1 and r 2 are used to level shift th e input and output to provide the largest output swing. r f and r g set the ac gain. c 2 isolates the virtual ground potential. r t and r 3 are the termination resistors for the line. c 1 , c 2 and c 3 are selected big enough to minimize the droop of the luminance signal. figure 28. sync pulse remover 5v 1k v out v in 75 ? + - 75 ? 1k 75 ? v s+ v s- figure 29. video signal 1v 0.5v 0v 1v 0.5v 0v m = 10s/div v out v in figure 30. two to one multiplexer +2.5v 1k 2mhz 75 ? + - 1k 75 ? -2.5v v out 75 ? 1v p-p b +2.5v 1k 2mhz + - 1k 75 ? -2.5v 2v p-p a enable figure 31. enable signal 0v -0.5v -1.5v -2.5v 1v 0v m = 50ns/div a enable b -1v
EL8300 fn7347 rev 2.00 page 12 of 14 may 20, 2005 figure 32. 5v single supply non inverting video line driver 5v r f v out v in 75 ? + - 75 ? 1k ? 75 ? c 3 470f r 3 c 1 47f r t 10k 10k r 2 r 1 1k ? r g c 2 220f figure 33. 5v single supply inverting video line driver 5v r f v out v in 75 ? - + 75 ? 500 ? 75 ? c 3 470f r 3 c 1 47f r t 10k 10k r 2 r 1 1k ? r g c 2 220f 5v figure 34. video line driver frequency response 5 4 3 2 1 0 -1 -2 -3 -4 -5 normalized gain (db) 100k 1m 10m 100m 200m frequency (hz) a v = -2 a v = 2
EL8300 fn7347 rev 2.00 page 13 of 14 may 20, 2005 so package outline drawing
fn7347 rev 2.00 page 14 of 14 may 20, 2005 EL8300 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2003-2005. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. qsop package outline drawing note: the package drawing shown here may not be the latest versi on. to check the latest revision , please refer to the intersil website at http://www.intersil.com/design/packages/index.asp

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